Processing technologies and device structures for forming integrated circuits (ICs) are implemented by using a plurality of interconnected field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs), or simply MOS transistors. A typical MOS transistor includes a gate electrode as a control electrode and spaced apart source and drain electrodes between which a current can flow. A control voltage applied to the gate electrode controls the flow of current through a channel between the source and drain electrodes. As the complexity of the integrated circuits increases, more and more MOS transistors are needed to implement the integrated circuit function. Thus, it becomes important to reduce the size of individual MOS transistors to achieve an integrated circuit that is reasonably sized and reliably manufacturable. Most importantly, reducing the size of IC increases the number of IC chips per wafer, which has become the most effective approach to reduce manufacture cost in semiconductor IC industry.
Wireless applications typically use a 4.5-5.5 V power MOSFET, when a ˜5V operational level is needed to preserve both signal swing range and signal-to-noise ratios. The requirement for deep submicron ˜5V power MOSFETs in 0.13 μm technology are the following: (1) low Rdson and high drive current (more than 50% scaling); (2) low off-state leakage current <1-10 pA/μm; (3) high reliability against hot carrier injection (HCI) damage; and (4) the restriction of process flows to 0.18 μm or 0.13 μm CMOS platforms.
Under current conditions, the manufacture of deep submicron ˜5V power MOSFETs in 0.13 μm technology platform could face major challenges if conventional structures widely used for 0.5 μm (or above) platforms are adopted. For instance, conventional spacer-based MOSFETs with a lightly doped drain (LDD) have a channel length limit of ˜0.5 μm due to reliability issues caused by HCI damage. To sufficiently reduce the damage when operated at 5V, the gate length would have to increase to 0.5 μm or above. In addition, conventional halo-source (HS-GOLD) and gate-overlapped LDD drain (GOLD) MOSFETs can be shrunk down to deep submicron, but the operation voltage has to be lowered below 3.5 V due to both HCI and punchthrough issues. Better HCI performance requires longer GOLD, which requires extra thermal drive-in cycles. This is not possible in the 0.13 μm CMOS process flow where the thermal budget is very limited
Conventional LDMOS (Lateral double diffused MOS) can operate at a higher voltage, however, two major difficulties in the fabrication process prevent the scaling down of an LDMOS to deep submicron region. In one type of LDMOS processing, the channel length is defined by non-self-aligned ion implant. To meet lithography requirements for misalignment tolerances, a sufficient margin has to be considered, which sets a limit of ˜0.5 μm for this type of LDMOS. In a second type of LDMOS processing, the channel doping is carried out first by a self-aligned implantation with poly gate serving as a mask, and then by subsequent thermal drive-in to diffuse the dopant into the channel. Although this type of LDMOS provides a smaller device, the use of an extra thermal drive-in cycle is not compatible with standard 0.13 μm CMOS process flow where thermal budget is very limited. Typically this type of LDMOS may not be fabricated in any advanced CMOS-based technology platform.
It is concluded that conventional structures for ˜5V MOSFETs used in 0.5 μm platforms are not capable of scaling to below 0.5 μm either due to fabrication processing issues (thermal budget or misalignment) or due to device reliability issues (HCI or punchthrough). Accordingly, it is desirable to provide a new type of deep submicron semiconductor device, and more particularly deep submicron power MOSFET with an operation voltage of ˜5 V. In addition, it is desirable to provide a method for fabricating a deep submicron power MOSFET that allows for operation in the ˜5V range without incurring any additional process steps when building in the 0.13 μm technology platform. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.